In data transmission applications, delay elements are frequently used for clock synchronization, clock multiplication and clock/data recovery. In recent years digital technique's are displacing the analogue circuits which have been used in data recovery such as analogue phase locked loops. Digital techniques which enable selection of a variable delay length path through a plurality of short fixed time delay elements is being used to construct time delays used in data recovery circuits. This short fixed time delay element is typically provided by the propagation time of a signal through field effect transistors which are cascaded to achieve the desired length of delay. However, the delay value provided by these transistors are not stable enough for precise applications. The delay is a function of the manufacturing process and can vary as a function of the temperature and the power supply conditions.
One solution to this problem is to calibrate the delay and to design and include compensation circuits in the same circuit. Another approach would be to provide a method for measuring the delay and adjusting the delays in such circuits. Accordingly, delay circuits are needed in which pulse delays are measured and adjustable in response thereto.
Another problem in data recovery circuits relates to DC balance problems which requires modification of the duty cycle of serial data. This balance problem can result in errors in data recovery if the data is sampled at the wrong time as a result of duty cycle distortion. All of these problems can be corrected by delay techniques which can selectively and independently modify the rising edge and falling edge delays of a pulse transition.